For example, Japanese Patent Application Laid-Open Publication No. 2007-213375 (Patent Document 1), No. 2009-223854 (Patent Document 2), and No. 2010-123203 (Patent Document 3) describe configurations in which a memory device, and a controller device which accesses the memory device are mounted on a wiring substrate. In Patent Document 1, the memory device and the controller device are connected with each other in wiring layers L1 and L2 of the wiring substrate. In Patent Documents 2 and 3, the memory device and the controller device are connected in wiring layers L1, L3 and L6 of the wiring substrate. JEDEC Standard JESD209-4 (Non Patent Document 1) defines the LPDDR4 standard.